1. Field of the Invention
Embodiments of the invention relate to power and performance in computer memory systems. More specifically, embodiments of the invention relate to providing a clocking signal within a memory subsystem.
2. Background
The power performance relationship in the personal computer (PC) environment continues to pressure platform designers to improve power at minimal cost. Unfortunately, to accommodate legacy dynamic random access memory (DRAM) using the industry standard double data rate 2 (DDR2) feature set early fully buffered dual in line memory modules (DIMM) (FBD) require higher power levels and prior evolutionary approaches as a result of the addition of a buffer chip. This feature set is defined in JEDEC Standard DDR2 SDRAM Specification JESD79-2A, published January 2004 (the DDR2 Standard). Moreover, the DDR2 feature set limited the ability to enable features in the buffer-DRAM interface to reduce power and improve performance at lower cost.
Existing designs use an architecture with bi-directional strobes generated from the buffer chip to the DRAM. In this design, one output strobe is required per DRAM, the strobe design results in timing problems at higher speeds which is due to the uncertainty caused by drift effects between issue commands and N unit intervals until it is executed. While a steady state clock eliminates this uncertainty, it would cause the pin count to increase by two times at both the DRAM and the buffer chip. Such increased pin count results in increased cost and power dissipation.